Metal interconnect structures are an important part of VLSI integrated circuits. The metal interconnect structures typically include metal lines and vias. The vias are used to interconnect the metal lines with conductive structures above and below the metal interconnect layer. Sophisticated ICs may include several layers of metal interconnect structures. The metal lines are commonly used on VLSI integrated circuits for carrying digital signals, analogs signals, or bias power to and from the embedded semiconductor devices.
As integration densities increase, and feature sizes decrease, the aspect ratio of the gaps between adjacent metal lines increases. Currently, the aspect ratios of the gaps between adjacent metal lines are approaching two. For example, the height of a metal line may be on the order of 1.0 microns, whereas the spacing between the metal lines may approach 0.5 microns.
Typically, after the metal lines have been formed through metal etching, a dielectric layer is deposited over the metal lines for insulation purposes. This dielectric layer is referred to as either an intermetal dielectric (IMD), or an interlayer dielectric (ILD). The insulating dielectric layer typically is formed from a composite of multiple layers of oxide. For example, in many processes, the insulative dielectric layer comprises a bulk oxide layer followed by a cap oxide layer.
As the aspect ratios of the gaps between metal lines increases, it has been found that conventional chemical vapor deposition of oxides oftentimes fail to exhibit acceptable gap filling characteristics. Imperfections and discontinuities such as keyholes and incomplete filling occur.
One type of oxide that has demonstrated encouraging gap filling capabilities is the high density plasma chemical vapor deposition (HDPCVD) oxide. HDPCVD oxide technology has only been recently developed in the past few years. Thus, although HDPCVD oxide remains a promising gap filling alternative for high aspect ratio gaps, difficulties have been found in the practical application of the HDPCVD oxide technology.
For example, tuning to FIG. 1, a phenomena known as "corner clipping" occurs during deposition of the HDPCVD oxide. In FIG. 1, metal lines 103 are formed atop a substrate 101. The substrate 101 is understood to possibly include a semiconductive wafer, active and passive devices formed within the wafer, and layers formed on the wafers surface. Thus, the term "substrate" is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.
The metal lines 103 are typically formed from either copper or aluminum. Atop the metal line 103 is a titanium nitride layer 105. As is known by those of ordinary skill in the art, the titanium nitride layer 105 is commonly used as an anti-reflection coating (ARC) during the etching of the metal lines 103.
When a gap filling HDPCVD oxide 107 is deposited over the titanium nitride layer 105 and the metal lines 103, the corners of the titanium nitride layer 105 along the edges of the metal lines 103 exhibit erosion, which is referred to as corner clipping. Thus, the HDPCVD oxide layer 107, while filling the gaps between the metal lines 103, tends to erode the corners of the titanium nitride layer 105. This phenomena has been particularly seen using the Applied Materials model Ultima 5200 HDPCVD Century ("Ultima") apparatus. The corner clipping effect raises additional issues during later process integration steps.
The mechanism by which the HDPCVD oxide is formed is by a combination of deposition and sputtering (also known as "sputter-etch" or simply "etch" in the art). The deposition process of the Ultima apparatus results from a low frequency RF power source that drives the silicon (from silane) and oxygen ions towards the surface of the wafer to form a silicon oxide. The sputtering process of the Ultima apparatus results from a high frequency bias power that drives inert gas ions (typically argon) towards the surface of the wafer. As can be appreciated by those skilled in the art, sputtering in the HDPCVD oxide art refers to the process of bombarding deposited oxide with inert gas ions in order to dislodge oxide particles. Thus, the deposition process forms oxide on the wafer and the sputtering process dislodges and rearranges the deposited oxide on the wafer.
By varying the deposition-to-sputter ratio (D/S), different gap filling properties may be achieved. For high aspect ratio gaps, typically, an aggressive D/S ratio is used to fill the gaps. For example, it is not uncommon for a D/S ratio of 3 to be used with the Ultima apparatus. However, as seen in FIG. 1, this particular "recipe" results in corner clipping. Another disadvantage of this low D/S ratio is that the throughput is relatively low. In other words, it requires a relatively long time to achieve the formation of the HDPCVD oxide.
It has been contemplated to use a two-step process for the formation of the HDPCVD oxide. However, this approach has also shown limited success. For example, turning to FIG. 2, experiments have indicated that the two-step process of forming the HDPCVD oxide gives rise to vertical seams 109 that will cause difficulties when a later cap oxide layer is deposited. The vertical seams 109 are due to the uneven gap filling from the center to the edge of a wafer. In most cases, the edge area of the wafer has the gap filling beneath the top of the metal line. Further, there is a sharp interface between the first HDPCVD oxide layer 111 and the second HDPCVD oxide layer 113. The sharp interface also tends to weaken the integrity of the HDPCVD oxide. Moreover, other imperfections, voids, and gaps 115 also have been shown to arise.
The vertical seams 109 are particularly prevalent at the peripheral regions of a wafer. This is believed to result from the well-known effect of having uneven oxide deposition thicknesses over the wafer surface. This is believed to result from the gas nozzle design of the currently commercially available HDPCVD systems.
The present invention is directed towards a method of depositing HDPCVD oxide into high aspect ratio gaps in such a manner so as to eliminate the problems of the prior art.